Alternator and rectifier thereof for preventing reverse current

ABSTRACT

An alternator and a rectifier thereof are provided. The rectifier includes a transistor and a gate voltage control circuit. The transistor is controlled by a gate voltage. The gate voltage control circuit generates the gate voltage according to a voltage difference between an input voltage and a rectified voltage. During a first time interval after the voltage difference drops to a first preset threshold voltage, the gate voltage control circuit determines whether the voltage difference is less than a second preset threshold voltage, and decides whether to provide the gate voltage to turn on the transistor. When the transistor is turned on, the voltage difference substantially equals to a first reference voltage. And during a second time interval, the gate voltage control circuit regulates the gate voltage to set the voltage difference substantially to a second reference voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 109136195, filed on Oct. 20, 2020. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND Technical Field

The disclosure relates to an alternator and a rectifier, particularly toan alternator and a rectifier capable of preventing reverse current.

Description of Related Art

In an AC generator, a rectifier is often adapted to rectify the AC inputvoltage to generate a rectified voltage that can be regarded as a DCvoltage. Conventionally, diodes or transistors are often adapted torectify the input voltage. Ideally, during the negative half wave of therectified voltage, the voltage value remains equal to the referencevoltage (for example, 0 volt). However, in actual situations such as theconventionally known rectified voltage as shown in the waveform diagramof FIG. 1 , the voltage value of the input voltage of the rectifiedvoltage having a voltage VP as the peak value is less than the referencevoltage VO in its negative half wave TN. In other words, power is lossin the negative half wave TN of the input voltage, decreasing theoperational efficiency of the system.

In addition, there are related technologies in the prior art thatperform rectification of the input voltage by controlling the timing ofturning on the transistor. However, in practical applications, thewaveform of the rectified voltage and the timing of turning on thetransistor must be in cooperation with each other. If the timing ofturning on the transistor is too late or too early, a reverse currentmay occur.

SUMMARY

The disclosure provides an alternator and a rectifier thereof, adaptedto prevent the occurrence of reverse current during rectification.

The rectifier includes a transistor and a gate voltage control circuit.The transistor has a first end receiving an input voltage, a second endgenerating a rectified voltage, and a control end receiving a gatevoltage. The gate voltage control circuit is coupled to the transistorand generates the gate voltage according to the voltage differencebetween the input voltage and the rectified voltage. During a first timeinterval after the voltage difference drops to a first preset thresholdvoltage, the gate voltage control circuit determines whether the voltagedifference is less than a second preset threshold voltage, and decideswhether to provide the gate voltage to turn on the transistor. When thetransistor is turned on, the voltage difference substantially equals toa first reference voltage. And during a second time interval after thefirst time interval, the gate voltage control circuit regulates the gatevoltage to set the voltage difference substantially to a secondreference voltage.

The rectifier includes a transistor and a gate voltage control circuit.The transistor has a first end receiving an input voltage, a second endgenerating a rectified voltage, and a control end receiving a gatevoltage. The gate voltage control circuit is coupled to the transistorand generates the gate voltage according to the voltage differencebetween the input voltage and the rectified voltage. During a first timeinterval after the voltage difference drops to a first preset thresholdvoltage, the gate voltage control circuit determines whether the voltagedifference is less than a second preset threshold voltage, and decideswhether to provide the gate voltage to turn on the transistor. When thetransistor is turned on, during the first time interval and the secondtime interval which is after the first time interval, when the voltagedifference rises to a third preset threshold voltage, the gate voltageis regulated to turn off the transistor. During the first time interval,the third preset threshold voltage is greater than or equal to zero. Andduring the second time interval, the third preset threshold voltage isless than or equal to zero.

The alternator of the present disclosure includes a rotor, a stator, andmultiple rectifiers as described above. Each of the rectifiers receivesa corresponding AC input voltage as the rectified voltage, and therectifiers together generate the rectified voltage.

In light of the above, during the first time interval after the voltagedifference between the input voltage and the rectified voltage drops tothe relatively high first preset threshold voltage, the gate voltagecontrol circuit of the present disclosure determines whether the voltagedifference drops lower to the relatively low second preset thresholdvoltage, and decides accordingly whether to fully turn on thetransistor. This way, the reverse current caused by turning on thetransistor too slowly may be prevented, thereby improving the overallperformance of the rectifiers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a waveform of the rectified voltage as conventionally known.

FIG. 2 is a schematic view of a rectifier according to an embodiment ofthe present disclosure.

FIG. 3A is a waveform of an implementation of a rectifier according toan embodiment of the present disclosure.

FIG. 3B is an enlarged diagram showing the zone Z1 in the waveform ofFIG. 3A of the present disclosure.

FIG. 4 is a waveform of a third preset threshold voltage of a rectifieraccording to an embodiment of the present disclosure.

FIG. 5A and FIG. 5B are waveforms of two different implementations ofrectifiers according to embodiments of the present disclosure.

FIG. 6 is a schematic view of a gate voltage control circuit accordingto an embodiment of the present disclosure.

FIG. 7 is a schematic view of an implementation of a signal generator ina gate voltage control circuit according to an embodiment of the presentdisclosure.

FIG. 8 is a schematic view of a voltage generator in a gate voltagecontrol circuit according to an embodiment of the present disclosure.

FIG. 9 is a schematic view of an alternator according to an embodimentof the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

FIG. 2 is a schematic view of a rectifier according to an embodiment ofthe present disclosure. A rectifier 200 includes a transistor TD1 and agate voltage control circuit 210. The transistor TD1 has a first end E1receiving an input voltage VS, a second end E2 generating a rectifiedvoltage VD, and a control end receiving a gate voltage VG. In thisembodiment, the operation of the transistor TD1 is equivalent to a diodevia the gate voltage VG, in which the first end of the transistor TD1 isequivalent to the cathode of the diode, and the second end of thetransistor TD1 is equivalent to the anode of the diode.

The gate voltage control circuit 210 is coupled to the transistor TD1and is adapted to provide the gate voltage VG. The gate voltage controlcircuit 210 receives a voltage difference VDS between the input voltageVS and the rectified voltage VD, and generates the gate voltage VGaccording to the voltage difference VDS. To describe the gate voltage VGin more detail, please refer to FIG. 2 and FIG. 3A at the same time.FIG. 3A is a waveform of an implementation of a rectifier according toan embodiment of the present disclosure.

In this embodiment, the gate voltage control circuit 210 detects thevoltage difference VDS of the transistor TD1, and detects a time pointTP1 when the voltage difference VDS drops to a first preset thresholdvoltage Vx. After the time point TP1, the gate voltage control circuit210 initiates a counting operation for a first time interval PAL Then,the gate voltage control circuit 210 may determine whether the voltagedifference VDS of the transistor TD1 has dropped to a second presetthreshold voltage VDS_ON during the first time interval PA1, in whichthe second preset threshold voltage VDS_ON is less than the first presetthreshold voltage Vx. In this embodiment, during the first time intervalPA1, the gate voltage control circuit 210 determines a time point TP2 atwhich the voltage difference VDS of the transistor TD1 drops to thesecond preset threshold voltage VDS_ON, and the gate voltage controlcircuit 210 generates the gate voltage VG at the time point TP2 to turnon the transistor TD1. In this embodiment, the transistor TD1 at thistime is turned on fully.

In this embodiment, when the counting operation of the first timeinterval PA1 is initiated, the gate voltage control circuit 210 does notturn on the transistor TD1 immediately. The gate voltage control circuit210 continues to detect the voltage difference VDS during the first timeinterval PA1, and only turns on the transistor TD1 when the voltagedifference VDS is determined to drop to the second preset thresholdvoltage VDS_ON.

Note here that in the embodiment of the present disclosure, the firsttime interval PA1 may be a preset, limited time interval. The first timeinterval PA1 may be set according to the time length of the negativehalf wave of the voltage difference VDS. Therefore, the later the timepoint TP2 when the voltage difference VDS drops to the second presetthreshold voltage VDS_ON occurs, the shorter the time length for thetransistor TD1 to be turned on fully. In addition, if the gate voltagecontrol circuit 210 detects that the voltage difference VDS has notdropped to the second preset threshold voltage VDS_ON during the firsttime interval PA1, then the transistor TD1 is not fully turned on duringthis cycle.

Incidentally, taking the transistor TD1 as an N-type transistor as anexample, the gate voltage control circuit 210 can provide a gate voltageVG having a voltage value high enough to turn on the transistor TD1fully. When the transistor TD1 is turned on, via the rectification ofthe transistor TD1, the voltage difference VDS may be equal to a firstreference voltage VR1 which is the product of the on-state resistance ofthe transistor TD1 and the current flowing through the transistor TD1.Take the fully turned-on transistor TD1 as an example. The on-resistanceof the transistor TD1 is extremely low, such that the first referencevoltage VR1 may maintain at or close to 0 volt.

Then, during a second time interval PA2 after the first time intervalPA1, the gate voltage control circuit 210 sets the voltage differenceVDS to a second reference voltage VR2 by regulating the gate voltage VGto adjust the equivalent resistance provided by the transistor TD1. Inthe embodiment, the first reference voltage VR1 may be greater than thesecond reference voltage VR2. However, in other embodiments of thepresent disclosure, the first reference voltage VR1 may also be equal toor less than the second reference voltage VR2, and the presentdisclosure is not limited thereto.

FIG. 3B is an enlarged diagram showing the zone Z1 in the waveform ofFIG. 3A of the present disclosure. During a third time interval PA3after the second time interval PA2, when the gate voltage controlcircuit 210 detects that the voltage difference VDS rises from thesecond reference voltage VR2 to a third preset threshold voltageVDS_OFF, the gate voltage control circuit 210 regulates the gate voltageVG so that the transistor TD1 is turned off. In this embodiment, thegate voltage control circuit 210 regulates the gate voltage VG to avoltage value low enough to turn off the transistor TD1.

Incidentally, please refer to FIG. 4 , which illustrates a waveform ofan implementation of a rectifier according to another embodiment of thepresent disclosure. In FIG. 4 , during the first time interval PA1 andthe second time interval PA2, when the gate voltage control circuit 210detects that the voltage difference VDS rises to the third presetthreshold voltage VDS_OFF, the gate voltage control circuit 210regulates the gate voltage VG to turn off the transistor TD1. And thethird preset threshold voltage VDS_OFF is regulatable. In the presentembodiment, during the first time interval PA1, a third preset thresholdvoltage VDS_OFF is greater than or equal to zero. And during the secondtime interval PA2, the third preset threshold voltage VDS_OFF is lessthan or equal to zero.

Please refer to FIG. 2 , FIG. 5A, and FIG. 5B. FIG. 5A and FIG. 5B arewaveforms of two different implementations of rectifiers according toembodiments of the present disclosure. In FIG. 5A, a rectifier 200applied to the alternator is switched from a state S1 where therectified current is greater than 0 ampere to a state S2 where therectified current is 0 ampere. After the gate voltage control circuit210 detects the time point TP1 when the voltage difference VDS drops tothe first preset threshold voltage Vx, the gate voltage control circuit210 performs the counting the first time interval PA1. At the time pointTP2 which is after a period of time from the time point TP1, the gatevoltage control circuit 210 detects that the voltage difference VDSdrops to the second preset threshold voltage VDS_ON. The gate voltagecontrol circuit 210 provides the gate voltage VG correspondingly at thetime point TP2 so that the transistor TD1 is fully turned on. After atime point TP3 when the first time interval PA1 ends, the gate voltagecontrol circuit 210 performs the counting for the second time interval.In this embodiment, a time period PION during which the transistor TD1is fully turned on is shorter than the time period of the first timeinterval PA1.

In FIG. 5B, the gate voltage control circuit 210 detects that the timepoint TP2 at which the voltage difference VDS drops to the second presetthreshold voltage VDS_ON overlaps with the time point TP3 at which thefirst time interval PA1 ends (or, the time point TP2 is later than thetime point TP3). Therefore, in this embodiment, the transistor TD1 isnot turned on fully.

It can be seen from the implementation of FIG. 5B of the presentdisclosure that at the time point TP2 when the voltage difference VDSdrops to the second preset threshold voltage VDS_ON, the gate voltagecontrol circuit 210 may prevent the transistor TD1 from being fullyturned on at a time point relatively late in the time interval of thenegative half-wave of the voltage difference VDS. This way, it mayeffectively reduce the possibility of generating the reverse currentfrom the up-pull of the voltage difference VDS when the transistor TD1is turned on fully.

FIG. 6 is a schematic view of a gate voltage control circuit accordingto an embodiment of the present disclosure. A gate voltage controlcircuit 600 includes an operational amplifier OP1, a switch SW1, and aswitch SW2. The operational amplifier OP1 receives a voltage differenceVDS and an regulated voltage acting as a second reference voltage VR2,and generates a gate voltage VG at an output terminal OT according to acontrol signal EN_OPA to drive a corresponding transistor. In addition,the operational amplifier OP1 receives a power supply VA as anoperational power supply, and receives a voltage VSS as a referenceground voltage. The switch SW2 is connected in series between anoperating voltage VH and an output terminal OT. The switch SW2 is turnedon or off according to a control signal EN_SW2. The switch SW1 isconnected in series between the ground voltage VSS and the outputterminal OT. The switch SW1 is turned on or off according to a controlsignal EN_SW1.

In terms of operational details, during the first time interval, thegate voltage control circuit 600 disables the operational amplifier OP1via the control signal EN_OPA at the time point when the voltagedifference VDS is less than the second preset threshold voltage, andturns on the switch SW2 via the control signal EN_SW2 to pull up thegate voltage VG to the operating voltage VH. Meanwhile, the switch SW1is turned off according to the control signal EN_SW1. Then, during asecond time interval after the first time interval, the gate voltagecontrol circuit 600 turns off the switches SW2 and SW1 respectively viathe control signals EN_SW2 and EN_SW1, and activates the operationalamplifier OP1 via the control signal EN_OPA. During the second timeinterval, the operational amplifier OP1 controls the voltage differenceVDS to equal to the second reference voltage VR2 and provides the gatevoltage VG at the output terminal OT. Then, during the third timeinterval, the gate voltage control circuit 600 turns off the switch SW2via the control signal EN_SW2, and disables the operational amplifierOP1 via the control signal EN_OPA. Then, during the third time interval,the gate voltage control circuit 600 turns on the switch SW1 via thecontrol signal EN_SW1. Through the turned-on switch SW1, the gatevoltage VG is pulled down to the ground voltage VSS, and the transistorcorrespondingly driven is turned off.

Regarding the foregoing embodiments, the control signals EN_OPA, EN_SW1,and EN_SW2 may be generated by a control signal generator provided inthe gate voltage control circuit 600. Regarding the implementation ofthe control signal generator, please refer to FIG. 7 , which is aschematic view of an implementation of a signal generator in a gatevoltage control circuit of an embodiment of the present disclosure. InFIG. 7 , a control signal generator 700 is adapted to compare thevoltage difference VDS with the first voltage Vx (which is equivalent tothe first preset threshold voltage) and generate a first comparisonresult CMP1, and to compare the voltage difference VDS with a secondvoltage Vy or a third voltage Vz and generate a second comparison resultCMP2. The control signal generator 700 generates control signals EN_SW1,EN_SW2, and EN_OPA according to the first comparison result CMP1 and thesecond comparison result CMP2. The first voltage Vx≥the third voltageVz≥the second voltage Vy≥the second preset threshold voltage (as thesecond preset threshold voltage VDS_ON of the embodiment of FIG. 3 ),and the third voltage Vz≥the third preset threshold voltage (as thethird preset threshold voltage VDS_OFF of the embodiment of FIG. 3 ).

In terms of implementation details, the control signal generator 700includes a multiplexer 710, comparators 720 and 730, counters 740 and750, a calculator 760, and a logic circuit 770. The multiplexer 710receives the second voltage Vy and the third voltage Vz, and selects toprovide the second voltage Vy or the third voltage Vz to the counter 740according to the second comparison result CMP2. The comparator 730receives the voltage difference VDS and the first voltage Vx, andinitiates the counting operation of the counter 750 according to thecomparison result CMP1 when the voltage difference VDS drops to thefirst voltage Vx. The counter 750 receives a counting range value RGfrom the calculator 760, and counts the first time interval based on aclock signal CLK according to the counting range value RG. Thecomparator 720 is coupled to the multiplexer 710, and the comparator 720compares the voltage difference VDS with the voltage of the outputterminal of the multiplexer 710. In its initial state, the multiplexer710 selects to output the second voltage Vy to the comparator 720; thecomparator 720 compares the second voltage Vy with the voltagedifference VDS; and when the voltage difference VDS is equal to thesecond voltage Vy, the counter 740 initiates its counting operation.After the counter 740 initiates the counting operation, the multiplexer710 changes to select and output the third voltage Vz to the comparator720. When the voltage difference VDS is equal to the third voltage Vz,the comparator 720 stops the counter 740 from counting, and the count iscompleted. In this embodiment, the counter 740 is adapted to count thetime length of the negative half wave of the voltage difference VDS,which is approximately equal to the total sum of time of the first timeinterval and the second time interval.

And the calculator 760 receives the time length of the negative halfwave of the voltage difference VDS calculated by the counter 740, andmultiplies the received time length with a parameter a to produce thecounting range value RG. In this embodiment, the parameter a is apredetermined value smaller than 1.

In addition, in the embodiment of the present disclosure, the logiccircuit 770 is coupled to the counters 740 and 750. When the secondvoltage Vy is equal to the second preset threshold voltage, and that thethird voltage Vz is equal to the third preset threshold voltage, thelogic circuit 770 may perform logic operation according to the countingresults of the counters 740 and 750 as well as the start or halt stateof the counting operation, and generate the control signals EN_OPA,EN_SW1, and EN_SW2. To put it in detail, the logic circuit 770 mayrecognize whether it is in the first time interval or not according towhether the counting operation of the counter 750 is completed. When thecounting operation of the counter 750 has been initiated but yet to becompleted, and the counting operation of the counter 740 is initiated,the logic circuit 770 may enable the control signal EN_SW2. When thecounting operation of the counter 750 has been completed, and thecounting operation of the counter 740 has been initiated but yet to becompleted, the logic circuit 770 may enable the control signal EN_OPA.Also, when the counting operation of the counter 740 stops, the logiccircuit 770 may enable the control signal EN_SW1. At most one of thecontrol signals EN_SW1, EN_SW2, and EN_OPA is enabled.

On the other hand, regarding the implementations of FIG. 6 and FIG. 7 asmentioned above, the second reference voltage VR2, the first presetthreshold voltage Vx, the second preset threshold voltage VDS_ON, andthe third preset threshold voltage VDS_OFF may be generated by a voltagegenerator provided in the gate voltage control circuit 600. FIG. 8 is aschematic view of a voltage generator in a gate voltage control circuitaccording to an embodiment of the present disclosure. In FIG. 8 , avoltage generator 810 receives an operational power supply VHH, performsa voltage regulation operation according to the operational power supplyVHH, and generates the second reference voltage VR2, the first presetthreshold voltage Vx, the second preset threshold voltage VDS_ON, andthe third preset threshold voltage VDS_OFF. The operational power supplyVHH has a relatively high voltage value, and the voltage VSS is theground voltage. The voltage generator 810 may be a low drop-out (LDO)voltage regulator, or any other voltage regulation circuit known tothose with ordinary knowledge in the art, to which there is no certainlimit. The first preset threshold voltage Vx, the second presetthreshold voltage VDS_ON, and the third preset threshold voltage VDS_OFFgenerated by the voltage generator 810 may be adapted to implement thefirst voltage Vx, the second voltage Vy, and the third voltage Vz in theembodiment of FIG. 7 , respectively.

FIG. 9 is a schematic view of an alternator according to an embodimentof the present disclosure. An alternator 900 includes a rotor RT, astator ST, and a plurality of rectifiers 911 to 932. In this embodiment,the stator ST generates a plurality of phase voltages VU, VV, and VW.The phase voltages VU, VV, and VW are respectively provided to aplurality of rectifier circuits 910, 920, and 930 of different phases.The rectifier circuit 910 includes rectifiers 911 and 912 coupled inseries. The rectifier circuit 920 includes rectifiers 921 and 922coupled in series. And the rectifier circuit 930 includes rectifiers 931and 932 coupled in series. In this embodiment, the alternator 900 alsoincludes a resistor R1 (an equivalent load or an equivalent resistanceof a rechargeable battery) coupled in parallel and a capacitor C1 thatis an equivalent charging capacitor to generate a rectified outputvoltage close to a DC voltage.

The rectifiers 911 to 932 in this embodiment may be implemented byemploying the rectifier 200 of the foregoing embodiments. Relevantdetails have been described in the aforementioned embodiments andimplementations, which will not be repeated hereinafter.

In light of the above, the rectifier of the present disclosure startscounting the first time interval according to the first preset thresholdvoltage, and during the first time interval, determines whether thevoltage difference between the input voltage and the rectified voltagedrops to the second preset threshold voltage to determine whether toturn on the transistor fully. This way, the transistor is prevented frombeing turned on fully at too late a time point, and it may avoid thereverse current generated from the up-pull of the voltage differencewhen the transistor is fully turned on. And the system is ensured of itsnormal operation.

What is claimed is:
 1. A rectifier, comprising: a transistor, comprisinga first end receiving an input voltage, a second end generating arectified voltage, and a control end receiving a gate voltage; and agate voltage control circuit, coupled to the transistor, and generatingthe gate voltage according to a voltage difference between the inputvoltage and the rectified voltage, wherein during a first time intervalafter the voltage difference drops to a first preset threshold voltage,the gate voltage control circuit determines whether the voltagedifference is less than a second preset threshold voltage, and decideswhether to provide the gate voltage to turn on the transistor, whereinwhen the transistor is turned on, the voltage difference substantiallyequals to a first reference voltage, wherein the gate voltage controlcircuit counts a time length of a negative half wave of the voltagedifference, and multiplies the time length with a parameter to set thefirst time interval, and the parameter is a predetermined value lessthan 1; and during a second time interval after the first time interval,the gate voltage control circuit regulates the gate voltage to set thevoltage difference substantially to a second reference voltage.
 2. Therectifier according to claim 1, wherein the first preset thresholdvoltage is greater than the second preset threshold voltage, and thefirst reference voltage is greater than, less than, or equal to thesecond reference voltage.
 3. The rectifier according to claim 1, whereinduring the first time interval, the gate voltage control circuitprovides the gate voltage to turn on the transistor when determines thatthe voltage difference has been less than the second preset thresholdvoltage.
 4. The rectifier according to claim 1, wherein during the firsttime interval, the gate voltage control circuit provides the gatevoltage to turn off the transistor when determines that the voltagedifference has not been less than the second preset threshold voltage.5. The rectifier according to claim 1, wherein during a third timeinterval after the second time interval, when the voltage differencerises from the second reference voltage to a third preset thresholdvoltage, the gate voltage control circuit regulates the gate voltage toturn off the transistor.
 6. The rectifier according to claim 5, whereinthe gate voltage control circuit comprises: an operational amplifier,receiving the voltage difference and a regulated voltage, and generatingthe gate voltage at an output terminal according to a first controlsignal; a first switch, connected in series between a ground voltage andthe output terminal, and turned on or off according to a second controlsignal; and a second switch, connected in series between an operatingvoltage and the output terminal, and turned on or off according to athird control signal, wherein the regulated voltage is equal to thesecond reference voltage.
 7. The rectifier according to claim 6, whereinthe gate voltage control circuit further comprises: a control signalgenerator, comparing the voltage difference with a first voltage togenerate a first comparison result, comparing the voltage differencewith a second voltage or a third voltage to generate a second comparisonresult, and generating the first control signal, the second controlsignal, and the third control signal according to the first comparisonresult and the second comparison result, wherein the first voltage≥thethird voltage≥the second voltage≥the second preset threshold voltage,the third voltage≥the third preset threshold voltage, and the firstvoltage is equal to the first preset threshold voltage.
 8. The rectifieraccording to claim 7, wherein the control signal generator comprises: afirst comparator, generating the first comparison result by comparingthe voltage difference with the first voltage; a first counter, countingthe first time interval based on a clock signal according to the firstcomparison result and a counting range value; a multiplexer, selectingto output the second voltage or the third voltage according to thesecond comparison result; a second comparator, generating the secondcomparison result by comparing an output of the multiplexer with thevoltage difference; a second counter, generating a counting result byperforming a counting operation based on the clock signal according tothe second comparison result, wherein the counting result represents atotal sum of time of the first time interval and the second timeinterval; a calculator, coupled between the first counter and the secondcounter, and multiplying the counting result by the parameter to producethe counting range value; and a logic circuit, coupled to the firstcounter and the second counter, and generating the first control signal,the second control signal, and the third control signal according to thefirst time interval and the counting result.
 9. The rectifier accordingto claim 8, wherein the second counter initiates the counting operationwhen the voltage difference drops to the second voltage, and stops thecounting operation when the voltage difference rises to the thirdvoltage.
 10. The rectifier according to claim 7, wherein the gatevoltage control circuit further comprises: a voltage generator,generating the first preset threshold voltage, the second presetthreshold voltage, the third preset threshold voltage, the secondvoltage, the third voltage, and the second reference voltage accordingto an operational power supply.
 11. A rectifier, comprising: atransistor, comprising a first end receiving an input voltage, a secondend generating a rectified voltage, and a control end receiving a gatevoltage; and a gate voltage control circuit, coupled to the transistor,and generating the gate voltage according to a voltage differencebetween the input voltage and the rectified voltage, wherein during afirst time interval after the voltage difference drops to a first presetthreshold voltage, the gate voltage control circuit determines whetherthe voltage difference is less than a second preset threshold voltage,and decides whether to provide the gate voltage to turn on thetransistor, wherein when the transistor is turned on, during the firsttime interval and a second time interval which is after the first timeinterval, when the voltage difference rises to a third preset thresholdvoltage, the gate voltage is regulated to turn off the transistor,wherein: during the first time interval, the third preset thresholdvoltage is greater than or equal to zero; and during the second timeinterval, the third preset threshold voltage is less than or equal tozero, wherein the gate voltage control circuit counts a time length of anegative half wave of the voltage difference, and multiplies the timelength with a parameter to set the first time interval, and theparameter is a predetermined value less than
 1. 12. The rectifieraccording to claim 11, wherein the gate voltage control circuitcomprises: an operational amplifier, receiving the voltage differenceand a regulated voltage, and generating the gate voltage at an outputterminal according to a first control signal; a first switch, connectedin series between a ground voltage and the output terminal, and turnedon or off according to a second control signal; a second switch,connected in series between an operating voltage and the outputterminal, and turned on or off according to a third control signal; anda control signal generator, comparing the voltage difference with afirst voltage to generate a first comparison result, comparing thevoltage difference with a second voltage or a third voltage to generatea second comparison result, and generating the first control signal, thesecond control signal, and the third control signal according to thefirst comparison result and the second comparison result, wherein thefirst voltage≥the third voltage≥the second voltage≥the second presetthreshold voltage, the third voltage≥the third preset threshold voltage,and the first voltage is equal to the first preset threshold voltage.13. An alternator, comprising: a rotor; a stator, coupled to the rotor,and generating a plurality of AC voltages; and rectifiers according toclaim 1, wherein each of the rectifiers receives the corresponding ACvoltage as the input voltage, and the rectifiers together generate therectified voltage.
 14. An alternator, comprising: a rotor; a stator,coupled to the rotor, and generating a plurality of AC voltages; andrectifiers according to claim 11, wherein each of the rectifiersreceives the corresponding AC voltage as the input voltage, and therectifiers together generate the rectified voltage.